The Velox Transactional Memory Stack

Research output: Other contributionOtherContributedpeer-review

Contributors

  • Yehuda Afek - (Author)
  • Ulrich Drepper - (Author)
  • Pascal Felber - (Author)
  • Christof Fetzer - , Chair of Systems Engineering (Author)
  • Vincent Gramoli - (Author)
  • Michael Hohmuth - (Author)
  • Etienne Rivière - (Author)
  • Per Stenstrom - (Author)
  • Osman Unsal - (Author)
  • Derin Harmanci - (Author)
  • Patrick Marlier - (Author)
  • Stephan Diestelhorst - , Chair of Systems Engineering (Author)
  • Martin Pohlack - (Author)
  • Adrian Cristal - (Author)
  • Ibrahim Hur - (Author)
  • Aleksandar Dragojevic - (Author)
  • Rachid Guerraoui - (Author)
  • Michal Kapalka - (Author)
  • Sasa Tomic and Guy Korland - (Author)
  • Nir Shavit - (Author)
  • Martin Nowack - , Chair of Systems Engineering (Author)
  • Torvald Riegel - (Author)

Abstract

The adoption of multi- and many-core architectures for mainstream computing undoubtedly brings profound changes in the way software is developed. In particular, the use of fine grained locking as the multi-core programmer's coordination methodology is considered by more and more experts as a dead-end. The transactional memory (TM) programming paradigm is a strong contender to become the approach of choice for replacing locks and implementing atomic operations in concurrent programming. Combining sequences of concurrent operations into atomic transactions allows a great reduction in the complexity of both programming and verification, by making parts of the code appear to execute sequentially without the need to program using fine-grained locking. Transactions remove from the programmer the burden of figuring out the interaction among concurrent operations that happen to conflict when accessing the same locations in memory. The EU-funded FP7 VELOX project designs, implements and evaluates an integrated TM stack, spanning from programming language to the hardware support, and including runtime and libraries, compilers, and application environments. This paper presents an overview of the VELOX TM stack and its associated challenges and contributions.

Details

Original languageEnglish
Number of pages12
Volume30
Publication statusPublished - 2010
Peer-reviewedYes
No renderer: customAssociatesEventsRenderPortal,dk.atira.pure.api.shared.model.researchoutput.OtherContribution

Keywords

Research priority areas of TU Dresden

DFG Classification of Subject Areas according to Review Boards

Keywords

  • concurrent programming, software transactional memory, hardware transactional memory, compilers, language extensions, libraties, runtine, hardware, Java, Programming, Program processors