The challenge of ultra thin chip assembly

Research output: Contribution to book/Conference proceedings/Anthology/ReportConference contributionContributedpeer-review

Contributors

  • M Feil - , Fraunhofer Institute for Reliability and Microintegration (Author)
  • C Adler - , Fraunhofer Institute for Reliability and Microintegration (Author)
  • D Hemmetzberger - , Fraunhofer Institute for Reliability and Microintegration (Author)
  • M Konig - , Fraunhofer Institute for Reliability and Microintegration (Author)
  • Karlheinz Bock - , Fraunhofer Institute for Reliability and Microintegration (Author)

Abstract

Because of their low height, the low assembly topography and their mechanical flexibility, ultra thin chips (about 20mum) offer a wide field of possible applications. During the last years, the Fraunhofer-Institute for Reliability and Microintegration has successfully investigated in production, handling and assembly processes for such thin ICs. The chip handling and assembly processes had to be adopted to the very thin material, beginning with the development of special dicing by thinning process. A new pick and place process using thermal releasable tapes has been developed. For the chip assembly and contacting various methods depending on the application are available. This includes face up or face down variations. The complete process chain from wafer processing up to the assembled ultra thin IC together with some application examples are discussed in this paper.

Details

Original languageGerman
Title of host publication2004 Proceedings. 54th Electronic Components and Technology Conference
Place of PublicationLas Vegas
Pages35-40
Number of pages6
Publication statusPublished - 2004
Peer-reviewedYes
Externally publishedYes

Publication series

SeriesElectronic Components and Technology Conference (ECTC)
ISSN0569-5503

External IDs

Scopus 10444247340
ORCID /0000-0002-0757-3325/work/158767732

Keywords