The challenge of ultra thin chip assembly

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/GutachtenBeitrag in KonferenzbandBeigetragenBegutachtung

Beitragende

  • M Feil - , Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration (Autor:in)
  • C Adler - , Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration (Autor:in)
  • D Hemmetzberger - , Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration (Autor:in)
  • M Konig - , Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration (Autor:in)
  • Karlheinz Bock - , Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration (Autor:in)

Abstract

Because of their low height, the low assembly topography and their mechanical flexibility, ultra thin chips (about 20mum) offer a wide field of possible applications. During the last years, the Fraunhofer-Institute for Reliability and Microintegration has successfully investigated in production, handling and assembly processes for such thin ICs. The chip handling and assembly processes had to be adopted to the very thin material, beginning with the development of special dicing by thinning process. A new pick and place process using thermal releasable tapes has been developed. For the chip assembly and contacting various methods depending on the application are available. This includes face up or face down variations. The complete process chain from wafer processing up to the assembled ultra thin IC together with some application examples are discussed in this paper.

Details

OriginalspracheDeutsch
Titel2004 Proceedings. 54th Electronic Components and Technology Conference
ErscheinungsortLas Vegas
Seiten35-40
Seitenumfang6
PublikationsstatusVeröffentlicht - 2004
Peer-Review-StatusJa
Extern publiziertJa

Publikationsreihe

ReiheElectronic Components and Technology Conference (ECTC)
ISSN0569-5503

Externe IDs

Scopus 10444247340
ORCID /0000-0002-0757-3325/work/158767732