Software-Implemented Hardware Error Detection: Costs and Gains

Research output: Contribution to conferencesPaperContributedpeer-review

Contributors

Abstract

Commercial off-the-shelf (COTS) hardware is becoming less and less reliable because of the continuously decreasing feature sizes of integrated circuits. But due to economic constraints, more and more critical systems will be based on basically unreliable COTS hardware. Usually in such systems redundant execution is used to detect erroneous executions. However, arithmetic codes promise much higher error detection rates. Yet, they are generally assumed to generate very large slowdowns. In this paper, we assess and compare the runtime overhead and error detection capabilities of redundancy and several arithmetic codes. Our results demonstrate a clear trade-off between runtime costs and gained safety. However, unexpectedly the runtime costs for arithmetic codes compared to redundancy increase only linearly, while the gained safety increases exponentially.

Details

Original languageEnglish
Pages51-57
Number of pages7
Publication statusPublished - 2010
Peer-reviewedYes

Conference

TitleThe Third International Conference on Dependability
Abbreviated titleDEPEND 2010
Conference number
Duration18 - 25 July 2010
Website
Degree of recognitionInternational event
Location
CityVenedig
CountryItaly

External IDs

Scopus 77958003984

Keywords

Research priority areas of TU Dresden

DFG Classification of Subject Areas according to Review Boards

Keywords

  • arithmetic codes, hardware error detection, safety-critical systems, Safety, Registers, Redundancy, Runtime, Benchmark testing, safety-critical software