Software-Implemented Hardware Error Detection: Costs and Gains

Publikation: Beitrag zu KonferenzenPaperBeigetragenBegutachtung

Beitragende

Abstract

Commercial off-the-shelf (COTS) hardware is becoming less and less reliable because of the continuously decreasing feature sizes of integrated circuits. But due to economic constraints, more and more critical systems will be based on basically unreliable COTS hardware. Usually in such systems redundant execution is used to detect erroneous executions. However, arithmetic codes promise much higher error detection rates. Yet, they are generally assumed to generate very large slowdowns. In this paper, we assess and compare the runtime overhead and error detection capabilities of redundancy and several arithmetic codes. Our results demonstrate a clear trade-off between runtime costs and gained safety. However, unexpectedly the runtime costs for arithmetic codes compared to redundancy increase only linearly, while the gained safety increases exponentially.

Details

OriginalspracheEnglisch
Seiten51-57
Seitenumfang7
PublikationsstatusVeröffentlicht - 2010
Peer-Review-StatusJa

Konferenz

TitelThe Third International Conference on Dependability
KurztitelDEPEND 2010
Veranstaltungsnummer
Dauer18 - 25 Juli 2010
Webseite
BekanntheitsgradInternationale Veranstaltung
Ort
StadtVenedig
LandItalien

Externe IDs

Scopus 77958003984

Schlagworte

Forschungsprofillinien der TU Dresden

DFG-Fachsystematik nach Fachkollegium

Schlagwörter

  • arithmetic codes, hardware error detection, safety-critical systems, Safety, Registers, Redundancy, Runtime, Benchmark testing, safety-critical software