Software-Implemented Hardware Error Detection: Costs and Gains
Publikation: Beitrag zu Konferenzen › Paper › Beigetragen › Begutachtung
Beitragende
Abstract
Commercial off-the-shelf (COTS) hardware is becoming less and less reliable because of the continuously decreasing feature sizes of integrated circuits. But due to economic constraints, more and more critical systems will be based on basically unreliable COTS hardware. Usually in such systems redundant execution is used to detect erroneous executions. However, arithmetic codes promise much higher error detection rates. Yet, they are generally assumed to generate very large slowdowns. In this paper, we assess and compare the runtime overhead and error detection capabilities of redundancy and several arithmetic codes. Our results demonstrate a clear trade-off between runtime costs and gained safety. However, unexpectedly the runtime costs for arithmetic codes compared to redundancy increase only linearly, while the gained safety increases exponentially.
Details
Originalsprache | Englisch |
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Seiten | 51-57 |
Seitenumfang | 7 |
Publikationsstatus | Veröffentlicht - 2010 |
Peer-Review-Status | Ja |
Konferenz
Titel | The Third International Conference on Dependability |
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Kurztitel | DEPEND 2010 |
Veranstaltungsnummer | |
Dauer | 18 - 25 Juli 2010 |
Webseite | |
Bekanntheitsgrad | Internationale Veranstaltung |
Ort | |
Stadt | Venedig |
Land | Italien |
Externe IDs
Scopus | 77958003984 |
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Schlagworte
Forschungsprofillinien der TU Dresden
DFG-Fachsystematik nach Fachkollegium
Schlagwörter
- arithmetic codes, hardware error detection, safety-critical systems, Safety, Registers, Redundancy, Runtime, Benchmark testing, safety-critical software