SHRIMP: Efficient Instruction Delivery with Domain Wall Memory
Research output: Contribution to book/conference proceedings/anthology/report › Conference contribution › Contributed › peer-review
Contributors
Abstract
Domain Wall Memory (DWM) is a promising emerging memory technology but suffers from the expensive shifts needed to align memory locations with access ports. Previous work on DWM concentrates on data, while, to the best of our knowledge, techniques to specifically target instruction streams have not yet been studied. In this paper, we propose Shift-Reducing Instruction Memory Placement (SHRIMP), the first instruction placement strategy suited for DWM which is accompanied with a supporting instruction fetch and memory architecture. The proposed approach reduces the number of shifts by 40% in the best case with a small memory overhead. In addition, SHRIMP achieves a best case of 23% reduction in total cycle counts.
Details
Original language | English |
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Title of host publication | 2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) |
Publisher | IEEE Xplore |
ISBN (electronic) | 978-1-7281-2954-9 |
ISBN (print) | 978-1-7281-2955-6 |
Publication status | Published - Jul 2019 |
Peer-reviewed | Yes |
Publication series
Series | International Symposium on Low Power Electronics and Design (ISLPED) |
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ISSN | 1533-4678 |
Conference
Title | 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2019 |
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Duration | 29 - 31 July 2019 |
City | Lausanne |
Country | Switzerland |
External IDs
ORCID | /0000-0002-5007-445X/work/141545612 |
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