SHRIMP: Efficient Instruction Delivery with Domain Wall Memory

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/GutachtenBeitrag in KonferenzbandBeigetragenBegutachtung

Beitragende

Abstract

Domain Wall Memory (DWM) is a promising emerging memory technology but suffers from the expensive shifts needed to align memory locations with access ports. Previous work on DWM concentrates on data, while, to the best of our knowledge, techniques to specifically target instruction streams have not yet been studied. In this paper, we propose Shift-Reducing Instruction Memory Placement (SHRIMP), the first instruction placement strategy suited for DWM which is accompanied with a supporting instruction fetch and memory architecture. The proposed approach reduces the number of shifts by 40% in the best case with a small memory overhead. In addition, SHRIMP achieves a best case of 23% reduction in total cycle counts.

Details

OriginalspracheEnglisch
Titel2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)
Herausgeber (Verlag)IEEE Xplore
ISBN (elektronisch)978-1-7281-2954-9
ISBN (Print)978-1-7281-2955-6
PublikationsstatusVeröffentlicht - Juli 2019
Peer-Review-StatusJa

Publikationsreihe

ReiheInternational Symposium on Low Power Electronics and Design (ISLPED)
ISSN1533-4678

Konferenz

Titel2019 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2019
Dauer29 - 31 Juli 2019
StadtLausanne
LandSchweiz

Externe IDs

ORCID /0000-0002-5007-445X/work/141545612

Schlagworte

Forschungsprofillinien der TU Dresden

ASJC Scopus Sachgebiete