SHERLOCK: Scheduling Efficient and Reliable Bulk Bitwise Operations in NVMs

Research output: Contribution to book/Conference proceedings/Anthology/ReportConference contributionContributedpeer-review

Abstract

Bulk bitwise operations are commonplace in application domains such as databases, web search, cryptography, and image processing. The ever-growing volume of data and processing demands of these domains often result in high energy consumption and latency in conventional system architectures, mainly due to data movement between the processing and memory subsystems. Non-volatile memories (NVMs), such as RRAM, PCM and STT-MRAM, facilitate conducting bulk-bitwise logic operations in-memory (CIM). Efficient mapping of complex applications to these CIM-capable NVMs is non-trivial and can even lead to slowdowns. This paper presents Sherlock, a novel mapping and scheduling method for efficient execution of bulk bitwise operations in NVMs. Sherlock collaboratively optimizes for performance and energy consumption and outperforms the state-of-the-art by 10× and 4.6×, respectively.

Details

Original languageEnglish
Title of host publicationProceedings of the 61st ACM/IEEE Design Automation Conference, DAC 2024
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
ISBN (electronic)9798400706011
Publication statusPublished - 7 Nov 2024
Peer-reviewedYes

Publication series

SeriesProceedings - Design Automation Conference
ISSN0738-100X

Conference

Title61st ACM/IEEE Design Automation Conference
Abbreviated titleDAC 2024
Conference number61
Duration23 - 27 June 2024
Website
LocationMoscone West Center
CitySan Francisco
CountryUnited States of America

External IDs

ORCID /0000-0002-5007-445X/work/191036874
ORCID /0000-0001-9295-3519/work/191041739

Keywords

Sustainable Development Goals

Keywords

  • bulk-bitwise logic, Compute-in-memory, reliability, scheduling