SHERLOCK: Scheduling Efficient and Reliable Bulk Bitwise Operations in NVMs

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/GutachtenBeitrag in KonferenzbandBeigetragenBegutachtung

Abstract

Bulk bitwise operations are commonplace in application domains such as databases, web search, cryptography, and image processing. The ever-growing volume of data and processing demands of these domains often result in high energy consumption and latency in conventional system architectures, mainly due to data movement between the processing and memory subsystems. Non-volatile memories (NVMs), such as RRAM, PCM and STT-MRAM, facilitate conducting bulk-bitwise logic operations in-memory (CIM). Efficient mapping of complex applications to these CIM-capable NVMs is non-trivial and can even lead to slowdowns. This paper presents Sherlock, a novel mapping and scheduling method for efficient execution of bulk bitwise operations in NVMs. Sherlock collaboratively optimizes for performance and energy consumption and outperforms the state-of-the-art by 10× and 4.6×, respectively.

Details

OriginalspracheEnglisch
TitelProceedings of the 61st ACM/IEEE Design Automation Conference, DAC 2024
Herausgeber (Verlag)Institute of Electrical and Electronics Engineers (IEEE)
ISBN (elektronisch)9798400706011
PublikationsstatusVeröffentlicht - 7 Nov. 2024
Peer-Review-StatusJa

Publikationsreihe

ReiheProceedings - Design Automation Conference
ISSN0738-100X

Konferenz

Titel61st ACM/IEEE Design Automation Conference
KurztitelDAC 2024
Veranstaltungsnummer61
Dauer23 - 27 Juni 2024
Webseite
OrtMoscone West Center
StadtSan Francisco
LandUSA/Vereinigte Staaten

Externe IDs

ORCID /0000-0002-5007-445X/work/191036874
ORCID /0000-0001-9295-3519/work/191041739

Schlagworte

Ziele für nachhaltige Entwicklung

Schlagwörter

  • bulk-bitwise logic, Compute-in-memory, reliability, scheduling