RV-CAP: Enabling Dynamic Partial Reconfiguration for FPGA-Based RISC-V System-on-Chip
Research output: Contribution to book/Conference proceedings/Anthology/Report › Conference contribution › Contributed › peer-review
Contributors
Abstract
Partial reconfiguration is remaining the core technique to build adaptive systems-on-chip (SoCs) for modern FPGA architectures. Current support for reconfiguration management targets a few adaptive SoC architectures. Therefore, the adoption of a new instruction set architecture like RISC-V to manage the reconfiguration process requires the development of suitable reconfiguration management along with the needed hardware and software modules. In this work, we present a solution to enable partial reconfiguration for FPGA-based RISC-V SoC. The developed RV-CAP controller consists of hardware modules and a set of improved software drivers to ease the reconfiguration process from the RISC-V processor. Our dynamic partial reconfiguration controller achieves a high reconfiguration throughput of 398.1 MB/s with low resource utilization overhead. The proposed reconfiguration management is implemented and evaluated using Xilinx Kintex-7 FPGA with the ability to be portable for any other Xilinx FPGAs supporting partial reconfiguration. Our goal is to enable open-source soft-core RISC-V processors to manage and interact with reconfigurable hardware accelerators on FPGA-based SoCs.
Details
Original language | English |
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Title of host publication | 2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) |
Pages | 172-179 |
Number of pages | 8 |
ISBN (electronic) | 9781665435772 |
Publication status | Published - 2021 |
Peer-reviewed | Yes |
Workshop
Title | 2021 IEEE International Parallel and Distributed Processing Symposium Workshops |
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Abbreviated title | IPDPSW 2021 |
Duration | 17 - 21 May 2021 |
Degree of recognition | International event |
City | Portland |
Country | United States of America |
External IDs
ORCID | /0000-0001-5005-0928/work/131190578 |
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Scopus | 85114405850 |
ORCID | /0000-0003-2571-8441/work/142240557 |
Keywords
ASJC Scopus subject areas
Keywords
- Dynamic partial reconfiguration, Field programmable gate arrays (FP-GAs), RISC-V