RV-CAP: Enabling Dynamic Partial Reconfiguration for FPGA-Based RISC-V System-on-Chip
Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/Gutachten › Beitrag in Konferenzband › Beigetragen › Begutachtung
Beitragende
Abstract
Partial reconfiguration is remaining the core technique to build adaptive systems-on-chip (SoCs) for modern FPGA architectures. Current support for reconfiguration management targets a few adaptive SoC architectures. Therefore, the adoption of a new instruction set architecture like RISC-V to manage the reconfiguration process requires the development of suitable reconfiguration management along with the needed hardware and software modules. In this work, we present a solution to enable partial reconfiguration for FPGA-based RISC-V SoC. The developed RV-CAP controller consists of hardware modules and a set of improved software drivers to ease the reconfiguration process from the RISC-V processor. Our dynamic partial reconfiguration controller achieves a high reconfiguration throughput of 398.1 MB/s with low resource utilization overhead. The proposed reconfiguration management is implemented and evaluated using Xilinx Kintex-7 FPGA with the ability to be portable for any other Xilinx FPGAs supporting partial reconfiguration. Our goal is to enable open-source soft-core RISC-V processors to manage and interact with reconfigurable hardware accelerators on FPGA-based SoCs.
Details
Originalsprache | Englisch |
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Titel | 2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) |
Seiten | 172-179 |
Seitenumfang | 8 |
ISBN (elektronisch) | 9781665435772 |
Publikationsstatus | Veröffentlicht - 2021 |
Peer-Review-Status | Ja |
Workshop
Titel | 2021 IEEE International Parallel and Distributed Processing Symposium Workshops |
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Kurztitel | IPDPSW 2021 |
Dauer | 17 - 21 Mai 2021 |
Bekanntheitsgrad | Internationale Veranstaltung |
Stadt | Portland |
Land | USA/Vereinigte Staaten |
Externe IDs
ORCID | /0000-0001-5005-0928/work/131190578 |
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Scopus | 85114405850 |
ORCID | /0000-0003-2571-8441/work/142240557 |
Schlagworte
ASJC Scopus Sachgebiete
Schlagwörter
- Dynamic partial reconfiguration, Field programmable gate arrays (FP-GAs), RISC-V