RV-CAP: Enabling Dynamic Partial Reconfiguration for FPGA-Based RISC-V System-on-Chip

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/GutachtenBeitrag in KonferenzbandBeigetragenBegutachtung

Beitragende

Abstract

Partial reconfiguration is remaining the core technique to build adaptive systems-on-chip (SoCs) for modern FPGA architectures. Current support for reconfiguration management targets a few adaptive SoC architectures. Therefore, the adoption of a new instruction set architecture like RISC-V to manage the reconfiguration process requires the development of suitable reconfiguration management along with the needed hardware and software modules. In this work, we present a solution to enable partial reconfiguration for FPGA-based RISC-V SoC. The developed RV-CAP controller consists of hardware modules and a set of improved software drivers to ease the reconfiguration process from the RISC-V processor. Our dynamic partial reconfiguration controller achieves a high reconfiguration throughput of 398.1 MB/s with low resource utilization overhead. The proposed reconfiguration management is implemented and evaluated using Xilinx Kintex-7 FPGA with the ability to be portable for any other Xilinx FPGAs supporting partial reconfiguration. Our goal is to enable open-source soft-core RISC-V processors to manage and interact with reconfigurable hardware accelerators on FPGA-based SoCs.

Details

OriginalspracheEnglisch
Titel2021 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
Seiten172-179
Seitenumfang8
PublikationsstatusVeröffentlicht - 2021
Peer-Review-StatusJa

Workshop

Titel2021 IEEE International Parallel and Distributed Processing Symposium Workshops
KurztitelIPDPSW 2021
Dauer17 - 21 Mai 2021
BekanntheitsgradInternationale Veranstaltung
StadtPortland
LandUSA/Vereinigte Staaten

Externe IDs

ORCID /0000-0001-5005-0928/work/131190578
Scopus 85114405850
ORCID /0000-0003-2571-8441/work/142240557