To scale the performance of multi-processor systems, hierarchical architectures with hybrid interconnects are commonly employed. However, accurately predicting performance and energy consumption in such systems is challenging due to the vast design space resulting from numerous task mapping and routing strategies. This letter presents an overview of a three-dimensional architecture for a multi-chip platform with hybrid connections. It highlights various types of inter-core communication within the architecture and the associated routing techniques. To assess its performance in terms of energy consumption and the utilization of different interconnects, we employ a nearestneighbor (NN)-based online task mapping policy for allocating various applications. Overall, this platform could also be applied to other multiprocessor system-on-chip (MPSoC) architectures that utilize hybrid connections.