Rethinking on-chip DRAM cache for simultaneous performance and energy optimization

Research output: Contribution to book/Conference proceedings/Anthology/ReportConference contributionContributedpeer-review

Abstract

State-of-the-art DRAM cache employs a small Tag-Cache and its performance is dependent upon two important parameters namely bank-level-parallelism and Tag-Cache hit rate. These parameters depend upon the row buffer organization. Recently, it has been shown that a small row buffer organization delivers better performance via improved bank-level-parallelism than the traditional large row buffer organization along with energy benefits. However, small row buffers do not fully exploit the temporal locality of tag accesses, leading to reduced TagCache hit rates. As a result, the DRAM cache needs to be re-designed for small row buffer organization to achieve additional performance benefits. In this paper, we propose a novel tag-store mechanism that improves the Tag-Cache hit rate by 70% compared to existing DRAM tag-store mechanisms employing small row buffer organization. In addition, we enhance the DRAM cache controller with novel policies that take into account the locality characteristics of cache accesses. We evaluate our novel tag-store mechanism and controller policies in an 8-core system running the SPEC2006 benchmark and compare their performance and energy consumption against recent proposals. Our architecture improves the average performance by 21.2% and 11.4% respectively compared to large and small row buffer organizations via simultaneously improving both parameters. Compared to DRAM cache with large row buffer organization, we report an energy improvement of 62%.

Details

Original languageEnglish
Title of host publicationDesign, Automation & Test in Europe Conference & Exhibition (DATE), 2017
Place of PublicationLausanne
PublisherIEEE Xplore
Pages362-367
Number of pages6
ISBN (electronic)978-3-9815370-8-6, 978-3-9815370-9-3
ISBN (print)978-1-5090-5826-6
Publication statusPublished - 11 May 2017
Peer-reviewedYes

Publication series

SeriesDesign, Automation and Test in Europe Conference and Exhibition (DATE)
ISSN1530-1591

Conference

Title20th Design, Automation and Test in Europe, DATE 2017
Duration27 - 31 March 2017
CitySwisstech, Lausanne
CountrySwitzerland

External IDs

ORCID /0000-0002-5007-445X/work/141545568