REDCAP: Reconfigurable RFET-Based Circuits Against Power Side-Channel Attacks
Research output: Contribution to book/Conference proceedings/Anthology/Report › Conference contribution › Contributed › peer-review
Contributors
Abstract
Power attacks are effective side-channel attacks (SCAs) that exploit weaknesses in the physical implementation of a cryptographic circuit to extract its secret information like encryption key. In recent years, emerging technologies have unlocked new possibilities in designing effective SCA countermeasures with less overhead. Reconfigurable Field-Effect Transistors (RFETs) are a type of beyond-CMOS technology that can be configured at run-time to act as an NFET or PFET transistor and provide two or more independent gates. These features make RFETs potent candidates for implementing hardware security techniques like logic locking and SCA countermeasures. In this paper, we propose REDCAP, a method to add randomness to the power traces of a circuit, employing compact reconfigurable RFET-based gates to make the design resilient against power SCAs. First, we explain the construction and control of reconfigurable blocks with isofunctional configurations inside the circuit. Then, we provide an algorithm to efficiently compose the reconfigurable blocks with other circuit parts to minimize the overhead and enable designers to determine the granularity of the reconfiguration. To evaluate our approach, we performed a Correlation Power Attack (CPA) on the S-box of the Piccolo and PRESENT, two lightweight cryptographic circuits, and the results show that REDCAP can highly enhance the resilience of the circuit against power SCAs.
Details
Original language | English |
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Title of host publication | 2024 Design, Automation and Test in Europe Conference and Exhibition, DATE 2024 - Proceedings |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
ISBN (electronic) | 9798350348590 |
Publication status | Published - 2024 |
Peer-reviewed | Yes |
Publication series
Series | Proceedings -Design, Automation and Test in Europe, DATE |
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ISSN | 1530-1591 |
Conference
Title | 2024 Design, Automation and Test in Europe Conference and Exhibition |
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Abbreviated title | DATE 2024 |
Conference number | 27 |
Duration | 25 - 27 March 2024 |
Website | |
Location | Palacio De Congresos De Valencia |
City | Valencia |
Country | Spain |
External IDs
ORCID | /0000-0003-3814-0378/work/163295410 |
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Keywords
ASJC Scopus subject areas
Keywords
- Correlation Power Analysis, Hardware security, RFET, Side-channel attack