Reconfigurable thin-film transistors based on a parallel array of Si-nanowires

Research output: Contribution to journalResearch articleContributedpeer-review

Contributors

Abstract

The implementation of advanced electronic devices in the fourth industrial revolution era can be achieved with bottom-up grown silicon nanowire (Si-NW) based transistors. Here, we have fabricated reconfigurable Schottky-barrier (SB) thin-film transistors (TFTs) consisting of a parallel array of bottom-up grown single-crystalline Si-NWs and investigated in detail their device length dependent electrical performance and transport mechanism with current-voltage transport-map, key electrical parameters, and numerical simulation. In particular, the effective extension length (Lext_eff) limited significantly the overall conduction behavior of reconfigurable Si-NW SB-TFTs, such as ambipolarity, mobility, threshold voltage, and series resistance. This work provides important information for a better understanding of the physical operation of reconfigurable transistors with SB contacts and further optimization of their performance for implementing practical applications.

Details

Original languageEnglish
Article number124504
JournalJournal of applied physics
Volume129
Issue number12
Publication statusPublished - 28 Mar 2021
Peer-reviewedYes

External IDs

Scopus 85103370613

Keywords