Predicting Hardware Acceleration Through Object Caching in AMIDAR Processors

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Contributors

Abstract

Dynamically reconfigurable architectures offer the opportunity to migrate software into hardware functional units at runtime. Architectures derived from the AMIDAR model exhibit such possibilities. In previous work we have shown how to identify heavily used code sequences and have also shown that it might be interesting to synthesize hardware for a set of methods of one class and also cache the state of particular objects in the synthesized hardware. In this paper we discuss a method to identify such objects at runtime and present a heuristics to select caching candidates in order to make optimal use of the limited storage resources.

Details

Original languageEnglish
Title of host publicationARCS 2006 - 19th International Conference on Architecture of Computing Systems
Pages162-171
Number of pages10
Publication statusPublished - 2006
Peer-reviewedYes

Publication series

SeriesGI-Edition : lecture notes in informatics. Proceedings
VolumeP081
ISSN1617-5468

Conference

Title19th International Conference on Architecture of Computing Systems, ARCS 2006
Duration13 - 16 March 2006
CityFrankfurt, Main
CountryGermany

Keywords

ASJC Scopus subject areas