Predicting Hardware Acceleration Through Object Caching in AMIDAR Processors

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/GutachtenBeitrag in KonferenzbandBeigetragenBegutachtung

Beitragende

Abstract

Dynamically reconfigurable architectures offer the opportunity to migrate software into hardware functional units at runtime. Architectures derived from the AMIDAR model exhibit such possibilities. In previous work we have shown how to identify heavily used code sequences and have also shown that it might be interesting to synthesize hardware for a set of methods of one class and also cache the state of particular objects in the synthesized hardware. In this paper we discuss a method to identify such objects at runtime and present a heuristics to select caching candidates in order to make optimal use of the limited storage resources.

Details

OriginalspracheEnglisch
TitelARCS 2006 - 19th International Conference on Architecture of Computing Systems
Seiten162-171
Seitenumfang10
PublikationsstatusVeröffentlicht - 2006
Peer-Review-StatusJa

Publikationsreihe

ReiheGI-Edition : lecture notes in informatics. Proceedings
BandP081
ISSN1617-5468

Konferenz

Titel19th International Conference on Architecture of Computing Systems, ARCS 2006
Dauer13 - 16 März 2006
StadtFrankfurt, Main
LandDeutschland

Schlagworte

ASJC Scopus Sachgebiete