Power-Aware Computing Systems on FPGAs: A Survey
Research output: Contribution to conferences › Paper › Contributed › peer-review
Contributors
Abstract
A major concern with battery-operated devices is power-awareness and its appropriate computing. The power dissipation of such systems is usually considered a hardware problem. However, it can be solved by implementing power-aware techniques. Such algorithms have shown promise as an approach to dynamically adjust the power consumption of embedded systems within feasible ranges. One of the most popular power-saving techniques is Dynamic Voltage and Frequency Scaling (DVFS). Besides the power management, an accurate and fast power monitoring service is necessary on embedded platforms to reduce power consumption. In this paper, we provide an overview of power-aware computing platforms based on different application domains. It intends to summarize recently published research results related to power-aware computing architectures using Field Programmable Gate Arrays (FPGAs). We identify trends and highlight key future directions for power management techniques and power monitoring services.
Details
Original language | English |
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Pages | 45-51 |
Number of pages | 7 |
Publication status | Published - 2021 |
Peer-reviewed | Yes |
Conference
Title | 2021 31st International Conference on Field Programmable Logic and Applications |
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Abbreviated title | FPL 2021 |
Conference number | 31 |
Duration | 30 August - 3 September 2021 |
Location | online |
City | Dresden |
Country | Germany |
External IDs
ORCID | /0000-0003-2571-8441/work/142240504 |
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Scopus | 85125784897 |
Keywords
ASJC Scopus subject areas
Keywords
- FPGAs, Clock gating, DVFS, Fault diagnosis, Power estimator, Power gating