PANACA: An open-source configurable network-on-chip simulation platform
Research output: Contribution to book/conference proceedings/anthology/report › Conference contribution › Contributed
Network-on-Chip (NoC) is the central communication infrastructure of modern Multi-Processor Systems-on-Chip (MPSoCs), as the number of processing elements integrated on a single chip is continuously increasing. The exploration of the huge design space offered by novel NoC-based MPSoC architectures requires early and accurate system modeling and simulation. This paper introduces PANACA, an open-source highly configurable NoC simulator written in SystemC-TLM. PANACA enables fast simulation of MPSoCs using NoC-based architectures and is designed for a modular, flexible and precise modeling of network elements. It offers a wide set of accurate configurable parameters, such as topology, routing algorithm and flow control. The provided simulation and exploration management allows a detailed and automated evaluation of the huge design space.
|Title of host publication||Proceedings of the SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)|
|Number of pages||6|
|Publication status||Published - 26 Aug 2022|
ASJC Scopus subject areas
- Network-on-Chip, Simulator, SystemC TLM, heterogeneous MPSoC