PANACA: An open-source configurable network-on-chip simulation platform

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/GutachtenBeitrag in KonferenzbandBeigetragen

Beitragende

Abstract

Network-on-Chip (NoC) is the central communication infrastructure of modern Multi-Processor Systems-on-Chip (MPSoCs), as the number of processing elements integrated on a single chip is continuously increasing. The exploration of the huge design space offered by novel NoC-based MPSoC architectures requires early and accurate system modeling and simulation. This paper introduces PANACA, an open-source highly configurable NoC simulator written in SystemC-TLM. PANACA enables fast simulation of MPSoCs using NoC-based architectures and is designed for a modular, flexible and precise modeling of network elements. It offers a wide set of accurate configurable parameters, such as topology, routing algorithm and flow control. The provided simulation and exploration management allows a detailed and automated evaluation of the huge design space.

Details

OriginalspracheEnglisch
Titel2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI)
Seiten1-6
Seitenumfang6
ISBN (elektronisch)978-1-6654-8128-1
PublikationsstatusVeröffentlicht - 26 Aug. 2022
Peer-Review-StatusNein

Externe IDs

dblp conf/sbcci/HaaseGFG22
Mendeley e64ba05b-4192-3c07-994d-c636b0058e97
unpaywall 10.1109/sbcci55532.2022.9893260
Scopus 85141656154
ORCID /0000-0003-2571-8441/work/142240538
ORCID /0000-0002-8604-0139/work/142244840

Schlagworte

Schlagwörter

  • Network-on-Chip, Simulator, SystemC TLM, heterogeneous MPSoC