Optimized communication architecture of MPSoCs with a hardware scheduler: A system view
Research output: Contribution to book/conference proceedings/anthology/report › Conference contribution › Contributed › peer-review
Contributors
Abstract
With increasing complexity of MPSoCs, efficient runtime management of system resources becomes of vital importance for improving the system performance and energy efficiency. OSIP [1] - an operating system application-specific instruction-set processor - provides a promising solution to this. It delivers high computational performance to deal with dynamic task scheduling and mapping, while still being programmable. However, the distributed computation among the different processing elements introduces complexity to the communication architecture, which tends to become the bottleneck of such systems. In this work, we show a detailed analysis and optimization for the communication architecture of OSIP-based MPSoCs. In particular, the joint effects of OSIP and the communication architecture are investigated from the system point of view.
Details
Original language | English |
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Title of host publication | 2010 International Symposium on System-on-Chip Proceedings, SoC 2010 |
Pages | 163-168 |
Number of pages | 6 |
Publication status | Published - 2010 |
Peer-reviewed | Yes |
Externally published | Yes |
Conference
Title | 12th International Symposium on System-on-Chip 2010, SoC 2010 |
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Duration | 29 - 30 September 2010 |
City | Tampere |
Country | Finland |
External IDs
ORCID | /0000-0002-5007-445X/work/141545602 |
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