Optimized communication architecture of MPSoCs with a hardware scheduler: A system view

Research output: Contribution to book/conference proceedings/anthology/reportConference contributionContributedpeer-review

Contributors

  • Diandian Zhang - , RWTH Aachen University (Author)
  • Han Zhang - , RWTH Aachen University (Author)
  • Jeronimo Castrillon - , RWTH Aachen University (Author)
  • Torsten Kempf - , RWTH Aachen University (Author)
  • Gerd Ascheid - , RWTH Aachen University (Author)
  • Rainer Leupers - , RWTH Aachen University (Author)
  • Bart Vanthournout - , CoWare, Inc. (Author)

Abstract

With increasing complexity of MPSoCs, efficient runtime management of system resources becomes of vital importance for improving the system performance and energy efficiency. OSIP [1] - an operating system application-specific instruction-set processor - provides a promising solution to this. It delivers high computational performance to deal with dynamic task scheduling and mapping, while still being programmable. However, the distributed computation among the different processing elements introduces complexity to the communication architecture, which tends to become the bottleneck of such systems. In this work, we show a detailed analysis and optimization for the communication architecture of OSIP-based MPSoCs. In particular, the joint effects of OSIP and the communication architecture are investigated from the system point of view.

Details

Original languageEnglish
Title of host publication2010 International Symposium on System-on-Chip Proceedings, SoC 2010
Pages163-168
Number of pages6
Publication statusPublished - 2010
Peer-reviewedYes
Externally publishedYes

Conference

Title12th International Symposium on System-on-Chip 2010, SoC 2010
Duration29 - 30 September 2010
CityTampere
CountryFinland

External IDs

ORCID /0000-0002-5007-445X/work/141545602

Keywords