Optimized communication architecture of MPSoCs with a hardware scheduler: A system view
Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/Gutachten › Beitrag in Konferenzband › Beigetragen › Begutachtung
Beitragende
Abstract
With increasing complexity of MPSoCs, efficient runtime management of system resources becomes of vital importance for improving the system performance and energy efficiency. OSIP [1] - an operating system application-specific instruction-set processor - provides a promising solution to this. It delivers high computational performance to deal with dynamic task scheduling and mapping, while still being programmable. However, the distributed computation among the different processing elements introduces complexity to the communication architecture, which tends to become the bottleneck of such systems. In this work, we show a detailed analysis and optimization for the communication architecture of OSIP-based MPSoCs. In particular, the joint effects of OSIP and the communication architecture are investigated from the system point of view.
Details
Originalsprache | Englisch |
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Titel | 2010 International Symposium on System-on-Chip Proceedings, SoC 2010 |
Seiten | 163-168 |
Seitenumfang | 6 |
Publikationsstatus | Veröffentlicht - 2010 |
Peer-Review-Status | Ja |
Extern publiziert | Ja |
Konferenz
Titel | 12th International Symposium on System-on-Chip 2010, SoC 2010 |
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Dauer | 29 - 30 September 2010 |
Stadt | Tampere |
Land | Finnland |
Externe IDs
ORCID | /0000-0002-5007-445X/work/141545602 |
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