On-Chip Measurement System for Within-Die Delay Variation of Individual Standard Cells in 65-nm CMOS
Research output: Contribution to journal › Research article › Contributed › peer-review
Contributors
Abstract
New measurement system for characterizing within-die delay variations of individual standard cells is presented. The proposed measurement system are able to characterize rising and falling delay variations separately by directly measuring the input and output waveforms of individual gate using an on-chip sampling oscilloscope in 65 nm 1.2V CMOS process. Seven types of standard cells are measured with 60 DUTs for each type. Good correlations of within-die delay distributions between measured and Monte Carlo simulated results are observed. The measured results of rising and falling delay are of great use to the modeling of standard cell library of deep-submicrometer process. By virtue of the proposed scheme, the relationship between the rising and falling delay variations and the active area of the standard cells is experimentally shown for the first time.
Details
Original language | English |
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Article number | 5999753 |
Pages (from-to) | 1876-1880 |
Number of pages | 5 |
Journal | IEEE transactions on very large scale integration (VLSI) systems |
Volume | 20 |
Issue number | 10 |
Publication status | Published - 1 Oct 2012 |
Peer-reviewed | Yes |
External IDs
Scopus | 84864773705 |
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ORCID | /0000-0002-4152-1203/work/165453417 |
Keywords
Keywords
- Delay, System-on-a-chip, Semiconductor device measurement, Oscilloscopes