Minimizing the effects of tolerance faults on hardware realizations of cellular neural networks
Research output: Contribution to conferences › Paper › Contributed › peer-review
Contributors
Abstract
In this paper a procedure for minimizing the effects of tolerance faults in Cellular Neural Network (CNN) chips is presented. Therefore the simulation system SCNN was connected with the `CNN Prototyping System' (CPPS) for adjusting the parameter values of the cp300 CNN chip. Results showing the erroneous outputs of the VLSI chip are presented first, then a suitable way for adapting parameter directly to a CNN realization is presented.
Details
Original language | English |
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Pages | 385-390 |
Number of pages | 6 |
Publication status | Published - 1998 |
Peer-reviewed | Yes |
Externally published | Yes |
Conference
Title | Proceedings of the 1998 5th IEEE International Workshop on Cellular Neural Networks and Their Applications, CNNA |
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Duration | 14 - 17 April 1998 |
City | London, UK |
External IDs
ORCID | /0000-0001-7436-0103/work/142240255 |
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