Low Power Image Processing Applications on FPGAs Using Dynamic Voltage Scaling and Partial Reconfiguration

Research output: Contribution to conferences › Paper › Contributed › peer-review

Contributors

Details

Original languageEnglish
Pages64-69
Number of pages6
Publication statusPublished - 2018
Peer-reviewedYes

Conference

TitleConference on Design and Architectures for Signal and Image Processing
Abbreviated titleDASIP
Conference number
Duration10 October 2018
Location
City

External IDs

Scopus 85061382083

Keywords

Research priority areas of TU Dresden

Keywords

  • embedded systems, image processing, reconfigurable architectures, dynamic voltage scaling, adaptive dynamic runtime techniques, reconfigurable SoCs, dynamic partial reconfiguration target, FPGAs, TULIPP project, Hardware, Libraries, Task analysis, Field programmable gate arrays, Voltage control, Embedded systems, real-time, reconfigurable, low power, FPGA, Dynamic Partial Reconfiguration, field programmable gate arrays, power aware computing, system-on-chip, low power image processing applications, high-performance embedded platforms, embedded image processing systems, SDSoC image processing library, Image processing, Real-time systems, Dynamic Voltage Scaling, Debugging