Low Power Image Processing Applications on FPGAs Using Dynamic Voltage Scaling and Partial Reconfiguration

Publikation: Beitrag zu Konferenzen › Paper › Beigetragen › Begutachtung

Beitragende

Details

OriginalspracheEnglisch
Seiten64-69
Seitenumfang6
PublikationsstatusVeröffentlicht - 2018
Peer-Review-StatusJa

Konferenz

TitelConference on Design and Architectures for Signal and Image Processing
KurztitelDASIP
Veranstaltungsnummer
Dauer10 Oktober 2018
Ort
Stadt

Externe IDs

Scopus 85061382083

Schlagworte

Forschungsprofillinien der TU Dresden

Schlagwörter

  • embedded systems, image processing, reconfigurable architectures, dynamic voltage scaling, adaptive dynamic runtime techniques, reconfigurable SoCs, dynamic partial reconfiguration target, FPGAs, TULIPP project, Hardware, Libraries, Task analysis, Field programmable gate arrays, Voltage control, Embedded systems, real-time, reconfigurable, low power, FPGA, Dynamic Partial Reconfiguration, field programmable gate arrays, power aware computing, system-on-chip, low power image processing applications, high-performance embedded platforms, embedded image processing systems, SDSoC image processing library, Image processing, Real-time systems, Dynamic Voltage Scaling, Debugging