This work presents an integrated, fully differential limiting amplifier designed for broadband communication systems with data rates up to 100 Gbit/s. It offers a dc gain of 58 dB and a gain-bandwidth-product (GBWP) of 25.4 THz. At 50 Gbit/s the input dynamic range for a differential peak-to-peak voltage swing of 1 V is larger than 40 dB. The outputs rise time is 7.8 ps and the sensitivity, for a bit error rate of 10^-6, is below 7 mV. The circuit employs a combination of small-signal and large-signal feedback techniques to increase the GBWP and to reduce undesired non-linear signal distortion for data rates above 50 Gbit/s. The key feature for achieving the highest data rates, without impairing the small-signal performance, is the internal amplitude control. The total power consumption of the circuit is 365 mW from a single 4.3 V supply. The final chip occupies a total area of 0.67 mm and is manufactured in a 130 nm SiGe BiCMOS process with a transit frequency of 300 GHz.