Interface optimization for improved routability in chip-package-board co-design

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Contributors

Abstract

The simultaneous optimization of both pin assignment and pin routing for different hierarchy levels (chip, package, board) of an electronic system is a bottleneck in today's hierarchical co-design flows, typically requiring manual optimization strategies and multiple iterations. Specifically, a fast and finegrained evaluation of routability that considers all requirements between the different hierarchy levels is missing. In this paper we provide a comprehensive, fast method to evaluate the routability of interfaces in hierarchical systems based on a new probabilistic routability prediction. We implemented our methodology in an industrial design flow and achieved significant improvement in overall routing, including reduced manufacturing costs of chip-package-board co-designs.

Details

Original languageEnglish
Title of host publicationInternational Workshop on System Level Interconnect Prediction (SLIP) 2011
Number of pages8
Publication statusPublished - Jun 2011
Peer-reviewedYes

Conference

TitleInternational Workshop on System Level Interconnect Prediction 2011
Abbreviated titleSLIP 2011
Conference number13
Duration5 June 2011
CitySan Diego
CountryUnited States of America

External IDs

Scopus 84857229127