Influence Of Well Profile And Gate Length On The ESD Performance Of A Fully Silicided 0.25/spl mu/m Cmos Technology

Research output: Contribution to book/Conference proceedings/Anthology/Report › Conference contribution › Contributed › peer-review

Contributors

  • K. Bock - , Interuniversity Microelectronics Centre (imec) (Author)
  • C. Russ - , Interuniversity Microelectronics Centre (imec) (Author)
  • G. Badenes - , Interuniversity Microelectronics Centre (imec) (Author)
  • G. Groeseneken - , Interuniversity Microelectronics Centre (imec) (Author)
  • L. Deferm - , Interuniversity Microelectronics Centre (imec) (Author)

Details

Original languageEnglish
Title of host publicationProceedings Electrical Overstress/Electrostatic Discharge Symposium
PublisherIEEE
Pages308-315
Number of pages8
ISBN (print)1-878303-69-4
Publication statusPublished - 25 Sept 1997
Peer-reviewedYes
Externally publishedYes

Conference

TitleElectrical Overstress/Electrostatic Discharge Symposium 1997
Abbreviated titleEOS/ESD 1997
Conference number19
Duration23 - 25 September 1997
CitySanta Clara
CountryUnited States of America

External IDs

Scopus 0031332666
ORCID /0000-0002-0757-3325/work/146645119

Keywords

Keywords

  • Electrostatic discharge, CMOS technology, Silicides, Implants, Protection, Testing, Degradation, Silicidation, CMOS process, Breakdown voltage