Influence of well profile and gate length on the ESD performance of a fully silicided 0.25 μm CMOS technology

Research output: Contribution to journalResearch articleContributedpeer-review

Contributors

  • Karlheinz Bock - , Interuniversitair Micro-Elektronica Centrum (Author)
  • Christian Russ - , Interuniversitair Micro-Elektronica Centrum (Author)
  • Goncal Badenes - , Interuniversitair Micro-Elektronica Centrum (Author)
  • Guido Groeseneken - , Interuniversitair Micro-Elektronica Centrum (Author)
  • Ludo Deferm - , Interuniversitair Micro-Elektronica Centrum (Author)

Abstract

On electrostatic discharge (ESD) evaluation of a silicided 0.25 μm complementary metal-oxide-semiconductor (CMOS) technology is carried out by HBM, CDM, and TLP tests. Good ESD hardness and device performance are obtained by using retrograde-like well profiles. It is shown that devices with minimum gate length do not necessarily give the best ESD-results. This is due to a difference in failure mechanism between the shortest and the longer channel devices and possibly by a more homogeneous snapback of the slightly longer devices.

Details

Original languageEnglish
Pages (from-to)286-294
Number of pages9
Journal Electrical Overstress Electrostatic Discharge Symposium proceedings
Volume21
Issue number4
Publication statusPublished - 1998
Peer-reviewedYes
Externally publishedYes

External IDs

ORCID /0000-0002-0757-3325/work/139064818

Keywords

ASJC Scopus subject areas