Improving Technology Mapping for And-Inverter-Cones
Research output: Contribution to book/Conference proceedings/Anthology/Report › Conference contribution › Contributed › peer-review
Contributors
Abstract
AND-inverter-cones (AICs), proposed in 2012, offer a suitable alternative to Look-Up-Tables (LUTs) as the basic building block for FPGAs. They support tapping of multiple side outputs and are intrinsically fracturable which favours reduction of logic duplication. Unlike {k-inputs} LUTs, their area scales linearly with the number of inputs. Technology mapping is one of the crucial tasks to realize the full power of AIC-based FPGAs. However, the current state-of-the-art implementations suffers two main drawbacks as they do not account for the AIC properties fully: (i) The required time set for each node is suboptimal in the context of AIC and that impairs the mapping quality; (ii) they rely on priority cuts, which are unnecessarily runtime-intensive in the context of AIC mapping. To improve the mapping quality, we propose and proof a new method to calculate the maximal required time for each node purely based on its graph depth and height. We propose an asymptotically runtime-optimal in-memory direct cut selection method which leads to similar area numbers (~ 1% area overhead) as our reference priority cut implementation. Combining these improvements with a second area recovery round leads to a final area reduction of 16.4% and 3% for the MCNC and VTR benchmarks respectively as compared to our reference implementation of the latest known technology mapper, while leaving the delay unaltered.
Details
Original language | English |
---|---|
Title of host publication | 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) |
Publisher | IEEE |
Pages | 274-279 |
Number of pages | 6 |
ISBN (electronic) | 978-3-9819263-6-1 |
ISBN (print) | 978-1-6654-9637-7 |
Publication status | Published - 14 Mar 2022 |
Peer-reviewed | Yes |
Publication series
Series | Design, Automation and Test in Europe Conference and Exhibition (DATE) |
---|
Conference
Title | 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022 |
---|---|
Duration | 14 - 23 March 2022 |
City | Virtual, Online |
Country | Belgium |
External IDs
unpaywall | 10.23919/date54114.2022.9774544 |
---|