HW/SW Co-Design of the HOG algorithm on a Xilinx Zynq SoC
Research output: Contribution to journal › Research article › Contributed › peer-review
Contributors
Abstract
An accurate and fast human detection is a crucial task for a wide variety of applications such as automotive and person identification. The histogram of oriented gradients (HOG) algorithm is one of the most reliable and applied algorithms for this task. However the HOG algorithm is also a compute intensive task. This paper presents three different implementations using the Zynq SoC that consists of an ARM processor and an FPGA. The first uses OpenCV functions and runs on the ARM processor. A speedup of 249×is achieved due to several optimizations that are implemented in this OpenCV-based HOG approach. The second is a HW/SW Co-Design implemented on the ARM processor and the FPGA. The third is completely implemented on the FPGA and optimized for an FPGA implementation to achieve the highest performance for high resolution images (1920×1080). This implementation achieves 39.6 fps which is a speedup of 503.9× compared to the OpenCV-based approach and 2× compared to this implementation with optimizations. The HW/SW Co-Design achieves a speedup of approximately 9× compared to an original HOG implementation running on the ARM processor.
Details
Original language | English |
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Pages (from-to) | 50-62 |
Number of pages | 13 |
Journal | Journal of parallel and distributed computing |
Volume | 109 |
Publication status | Published - Nov 2017 |
Peer-reviewed | Yes |
External IDs
ORCID | /0000-0003-2571-8441/work/159607550 |
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Keywords
ASJC Scopus subject areas
Keywords
- FPGA, HOG algorithm, Human detection, HW/SW Co-Design, Image processing, Real-time, SDSoC, Xilinx Zynq