HW/SW Co-Design of the HOG algorithm on a Xilinx Zynq SoC

Publikation: Beitrag in FachzeitschriftForschungsartikelBeigetragenBegutachtung

Beitragende

Abstract

An accurate and fast human detection is a crucial task for a wide variety of applications such as automotive and person identification. The histogram of oriented gradients (HOG) algorithm is one of the most reliable and applied algorithms for this task. However the HOG algorithm is also a compute intensive task. This paper presents three different implementations using the Zynq SoC that consists of an ARM processor and an FPGA. The first uses OpenCV functions and runs on the ARM processor. A speedup of 249×is achieved due to several optimizations that are implemented in this OpenCV-based HOG approach. The second is a HW/SW Co-Design implemented on the ARM processor and the FPGA. The third is completely implemented on the FPGA and optimized for an FPGA implementation to achieve the highest performance for high resolution images (1920×1080). This implementation achieves 39.6 fps which is a speedup of 503.9× compared to the OpenCV-based approach and 2× compared to this implementation with optimizations. The HW/SW Co-Design achieves a speedup of approximately 9× compared to an original HOG implementation running on the ARM processor.

Details

OriginalspracheEnglisch
Seiten (von - bis)50-62
Seitenumfang13
FachzeitschriftJournal of parallel and distributed computing
Jahrgang109
PublikationsstatusVeröffentlicht - Nov. 2017
Peer-Review-StatusJa

Externe IDs

ORCID /0000-0003-2571-8441/work/159607550

Schlagworte

Schlagwörter

  • FPGA, HOG algorithm, Human detection, HW/SW Co-Design, Image processing, Real-time, SDSoC, Xilinx Zynq