HW/SW Co-design of an IEEE 802.11a/G Receiver on Xilinx Zynq SoC Using High-Level Synthesis

Research output: Contribution to book/Conference proceedings/Anthology/Report › Conference contribution › Contributed › peer-review

Contributors

Details

Original languageEnglish
Title of host publicationProceedings of the 8th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, HEART 2017
Number of pages6
Publication statusPublished - 2017
Peer-reviewedYes

Publication series

SeriesHEART: Highly Efficient Accelerators and Reconfigurable Technologies

Conference

Title8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies
Abbreviated titleHEART 2017
Conference number8
Duration7 - 9 June 2017
Location
CityBochum
CountryGermany

External IDs

ORCID /0000-0003-2571-8441/work/142240453
Scopus 85040659718