Hot carrier degradation modeling of short-channel n-FinFETs
Research output: Contribution to book/conference proceedings/anthology/report › Conference contribution › Contributed › peer-review
Contributors
Abstract
Figure 1(a) shows the degradation of the transfer characteristics of a typical FinFET with Wfin = 10 nm, measured at Vd = 0.03 V after HC stress at Vstress = 1.8 V for different stress times. The degradation of the device parameters Vt, η and on-state drain current is clearly observed. The positive Vt shift indicates the built-up of a negative charge in the gate dielectric. The negative charge can result either from electron trapping in the gate dielectric or from generation of acceptor-type interface traps. Figure 1(b) shows the transconductance gm degradation during HC stress. Degradation of the maximum gm is observed attributed to the interface degradation, with a simultaneous parallel gm shift due to charge injection into the gate dielectric bulk defects [4]. Using the relation SS=(kT/q).qDit/Cox for the subthreshold slope SS, where Cox is the gate oxide capacitance and kT is the thermal energy, from figure 1(a) the extracted interface trap density Dit changes from 4×1012 to 5.5×1012cm-2eV-1.
Details
Original language | English |
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Title of host publication | 2015 73rd Annual Device Research Conference (DRC) |
Publisher | Wiley-IEEE Press |
Pages | 183-184 |
Number of pages | 2 |
ISBN (print) | 978-1-4673-8134-5 |
Publication status | Published - 24 Jun 2015 |
Peer-reviewed | Yes |
Conference
Title | 2015 73rd Annual Device Research Conference (DRC) |
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Duration | 21 - 24 June 2015 |
Location | Columbus, OH, USA |
External IDs
Scopus | 84957627474 |
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Keywords
Keywords
- Stress, Degradation, Logic gates, FinFETs, Threshold voltage, Voltage measurement, Dielectrics