Figure 1(a) shows the degradation of the transfer characteristics of a typical FinFET with W_fin = 10 nm, measured at V_d = 0.03 V after HC stress at V_stress = 1.8 V for different stress times. The degradation of the device parameters V_t, η and on-state drain current is clearly observed. The positive V_t shift indicates the built-up of a negative charge in the gate dielectric. The negative charge can result either from electron trapping in the gate dielectric or from generation of acceptor-type interface traps. Figure 1(b) shows the transconductance g_m degradation during HC stress. Degradation of the maximum g_m is observed attributed to the interface degradation, with a simultaneous parallel g_m shift due to charge injection into the gate dielectric bulk defects [4]. Using the relation SS=(kT/q).qD_it/C_ox for the subthreshold slope SS, where C_ox is the gate oxide capacitance and kT is the thermal energy, from figure 1(a) the extracted interface trap density D_it changes from 4×10¹² to 5.5×10¹²cm^-2eV^-1.