High performance circuit techniques for dynamic OR gates

Research output: Contribution to book/conference proceedings/anthology/reportConference contributionContributedpeer-review


  • B. Kheradmand-Boroujeni - , University of Tehran (Author)
  • F. Aezinia - , University of Tehran (Author)
  • A. Afzali-Kusha - , University of Tehran (Author)


In this paper, two methods for high fan-in dynamic OR gates are proposed. The methods are called high-speed low-swing OR gate (HSLS-OR) and low-power selective evaluate OR gate (LPSE-OR). HSLS-OR contains separate parallel NMOS logic trees in which one controls the evaluation phase of the other ones. This leads to a low voltage swing in the dynamic capacitive nodes. In LPSE-OR, the NMOS logic tree is divided into several successive parts to prevent using strong keepers. Unnecessary parts are disabled in the evaluation phase for saving the power. (16, 32, and 64)-bit HSLS-OR and (32 and 64)-bit LPSE-OR gates are simulated using HSPICE in 65 nm bulk CMOS technology. Compared to the previous works, the new circuits show 34-48% better power delay product (PDP)


Original languageEnglish
Title of host publicationIEEE International Symposium on Circuits and Systems (ISCAS) 2006
PublisherIEEE Xplore
Number of pages4
ISBN (print)0-7803-9389-9
Publication statusPublished - May 2006
Externally publishedYes

Publication series

SeriesIEEE International Symposium on Circuits and Systems (ISCAS)


TitleIEEE International Symposium on Circuits and Systems 2006
Abbreviated titleISCAS 2006
Duration21 May - 24 June 2006
LocationKos International Convention Centre

External IDs

Scopus 34547303492


Research priority areas of TU Dresden