High performance circuit techniques for dynamic OR gates

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/GutachtenBeitrag in KonferenzbandBeigetragenBegutachtung

Beitragende

  • B. Kheradmand-Boroujeni - , University of Tehran (Autor:in)
  • F. Aezinia - , University of Tehran (Autor:in)
  • A. Afzali-Kusha - , University of Tehran (Autor:in)

Abstract

In this paper, two methods for high fan-in dynamic OR gates are proposed. The methods are called high-speed low-swing OR gate (HSLS-OR) and low-power selective evaluate OR gate (LPSE-OR). HSLS-OR contains separate parallel NMOS logic trees in which one controls the evaluation phase of the other ones. This leads to a low voltage swing in the dynamic capacitive nodes. In LPSE-OR, the NMOS logic tree is divided into several successive parts to prevent using strong keepers. Unnecessary parts are disabled in the evaluation phase for saving the power. (16, 32, and 64)-bit HSLS-OR and (32 and 64)-bit LPSE-OR gates are simulated using HSPICE in 65 nm bulk CMOS technology. Compared to the previous works, the new circuits show 34-48% better power delay product (PDP)

Details

OriginalspracheEnglisch
TitelIEEE International Symposium on Circuits and Systems (ISCAS) 2006
Herausgeber (Verlag)IEEE Xplore
Seiten3662-3665
Seitenumfang4
ISBN (Print)0-7803-9389-9
PublikationsstatusVeröffentlicht - Mai 2006
Peer-Review-StatusJa
Extern publiziertJa

Publikationsreihe

ReiheIEEE International Symposium on Circuits and Systems (ISCAS)
ISSN0271-4302

Konferenz

TitelIEEE International Symposium on Circuits and Systems 2006
KurztitelISCAS 2006
Dauer21 Mai - 24 Juni 2006
Webseite
OrtKos International Convention Centre
StadtKos
LandGriechenland

Externe IDs

Scopus 34547303492

Schlagworte

Forschungsprofillinien der TU Dresden