Hardware Failure Virtualization Via Software Encoded Processing

Research output: Contribution to conferencesPaperContributedpeer-review

Contributors

Abstract

In future, the decreasing feature size will make it
much more difficult to built reliable microprocessors. Economic
pressure will most likely result in the reliability of micro-
processors being tuned for the commodity market. Dedicated
reliable hardware is very expensive and usually slower than
commodity hardware. Thus, software implemented hardware
fault tolerance (SIHFT) will become essential for building safe
systems. Existing SIHFT approaches either are not broadly
applicable or lack the ability to reliably deal with permanent
hardware faults. In contrast, Forin [1] introduced the Vital Coded
Microprocessor which reliably detects transient and permanent
hardware failures, but is not applicable to arbitrary programs. It
requires a dedicated development process and special hardware.
We extend Forin’s Vital Code, so that it is applicable to arbitrary
binary code which enables us to apply it to existing binaries or
automatically during compile time. Furthermore, our approach
does not require special purpose hardware.

Details

Original languageEnglish
Pages977-982
Number of pages6
Publication statusPublished - 2007
Peer-reviewedYes

Conference

Title2007 5th IEEE International Conference on Industrial Informatics
Abbreviated titleINDIN 2007
Conference number5
Duration23 - 27 June 2007
Website
Degree of recognitionInternational event
CityWien
CountryAustria

External IDs

Scopus 39749134824

Keywords

Research priority areas of TU Dresden

DFG Classification of Subject Areas according to Review Boards

Keywords

  • hardware, Microprocessores, computer crashes, Resistance heating, Binary codes, Frequency, Lithography, Aerospace electronics, Software safety, Fault tolerant systems, electronic engineering computing, fault tolerant computing, hardware failure virtualization, software encoded processing, software implemented hardware fault tolerance