Hardware Failure Virtualization Via Software Encoded Processing

Publikation: Beitrag zu KonferenzenPaperBeigetragenBegutachtung

Beitragende

Abstract

In future, the decreasing feature size will make it
much more difficult to built reliable microprocessors. Economic
pressure will most likely result in the reliability of micro-
processors being tuned for the commodity market. Dedicated
reliable hardware is very expensive and usually slower than
commodity hardware. Thus, software implemented hardware
fault tolerance (SIHFT) will become essential for building safe
systems. Existing SIHFT approaches either are not broadly
applicable or lack the ability to reliably deal with permanent
hardware faults. In contrast, Forin [1] introduced the Vital Coded
Microprocessor which reliably detects transient and permanent
hardware failures, but is not applicable to arbitrary programs. It
requires a dedicated development process and special hardware.
We extend Forin’s Vital Code, so that it is applicable to arbitrary
binary code which enables us to apply it to existing binaries or
automatically during compile time. Furthermore, our approach
does not require special purpose hardware.

Details

OriginalspracheEnglisch
Seiten977-982
Seitenumfang6
PublikationsstatusVeröffentlicht - 2007
Peer-Review-StatusJa

Konferenz

Titel2007 IEEE 5th International Conference on Industrial Informatics
KurztitelINDIN 2007
Veranstaltungsnummer5
Dauer23 - 27 Juni 2007
Webseite
BekanntheitsgradInternationale Veranstaltung
StadtWien
LandÖsterreich

Externe IDs

Scopus 39749134824

Schlagworte

Forschungsprofillinien der TU Dresden

DFG-Fachsystematik nach Fachkollegium

Schlagwörter

  • hardware, Microprocessores, computer crashes, Resistance heating, Binary codes, Frequency, Lithography, Aerospace electronics, Software safety, Fault tolerant systems, electronic engineering computing, fault tolerant computing, hardware failure virtualization, software encoded processing, software implemented hardware fault tolerance