Functionality-Enhanced Logic Gate Design Enabled by Symmetrical Reconfigurable Silicon Nanowire Transistors
Research output: Contribution to journal › Research article › Contributed › peer-review
Contributors
Details
| Original language | English |
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| Pages (from-to) | 689 - 698 |
| Number of pages | 9 |
| Journal | IEEE transactions on nanotechnology |
| Volume | 14 |
| Issue number | 4 |
| Publication status | Published - 8 May 2015 |
| Peer-reviewed | Yes |
External IDs
| Scopus | 84949501082 |
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