Full-Stack Optimization for CAM-Only DNN Inference

Research output: Contribution to book/Conference proceedings/Anthology/ReportConference contributionContributedpeer-review

Abstract

The accuracy of neural networks has greatly improved across various domains over the past years. Their ever-increasing complexity, however, leads to prohibitively high energy demands and latency in von-Neumann systems. Several computing-in-memory (CIM) systems have recently been proposed to overcome this, but trade-offs involving accuracy, hardware reliability, and scalability for large models remain a challenge. Additionally, for some CIM designs, the activation movement still requires considerable time and energy. This paper explores the combination of algorithmic optimizations for ternary weight neural networks and associative processors (APs) implemented using racetrack memory (RTM). We propose a novel compilation flow to optimize convolutions on APs by reducing their arithmetic intensity. By leveraging the benefits of RTM-based APs, this approach substantially reduces data transfers within the memory while addressing accuracy, energy efficiency, and reliability concerns. Concretely, our solution improves the energy efficiency of ResNet-18 inference on ImageNet by 7.5× compared to crossbar in-memory accelerators while retaining software accuracy.

Details

Original languageEnglish
Title of host publication2024 Design, Automation and Test in Europe Conference and Exhibition, DATE 2024 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (electronic)9798350348590
Publication statusPublished - 2024
Peer-reviewedYes

Publication series

SeriesProceedings -Design, Automation and Test in Europe, DATE
ISSN1530-1591

Conference

Title2024 Design, Automation and Test in Europe Conference and Exhibition, DATE 2024
Duration25 - 27 March 2024
CityValencia
CountrySpain

External IDs

ORCID /0000-0002-5007-445X/work/173985262

Keywords

Sustainable Development Goals

ASJC Scopus subject areas

Keywords

  • Associative memory, compiler optimizations, neu-ral network, racetrack memories