FeFET based Logic-in-Memory: an overview

Research output: Contribution to book/Conference proceedings/Anthology/ReportConference contributionContributedpeer-review

Contributors

  • Cédric Marchand - , École centrale de Lyon (Author)
  • Ian O’Connor - , École centrale de Lyon (Author)
  • Mayeul Cantan - , École centrale de Lyon (Author)
  • Evelyn T. Breyer - , NaMLab - Nanoelectronic materials laboratory gGmbH (Author)
  • Stefan Slesazeck - , NaMLab - Nanoelectronic materials laboratory gGmbH (Author)
  • Thomas Mikolajick - , Chair of Nanoelectronics, NaMLab - Nanoelectronic materials laboratory gGmbH (Author)

Abstract

Emerging non-volatile memories are getting new interest in the system design community. They are used to design logic-in-memory circuits and propose alternatives to von-Neuman architectures. Hafnium oxide-based based ferroelectric memory technology, which is fully compatible with CMOS technologies is particularly interesting for logic-in-memory designs. Indeed, this compatibility leads to various possibilities for fine-grain logic in memory applications where the memory capable element is tightly integrated with the transistors in the system. Nonvolatile and energy efficient computing for Internet of things and embedded artificial intelligence are among the potential applications for this technology. In this article, we focus on ferroelectric field-effect transistors (FeFET) and present an overview of three different fine-grain logic-in-memory possibilities with FeFETs: custom operation designs, reconfigurable circuits and a hybrid memory element accessible by content or by address. All presented circuits have been designed within a test chip using 28nm technology provided by GLOBALFOUNDRIES.

Details

Original languageEnglish
Title of host publicationProceedings - 2021 16th International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2021
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Number of pages6
ISBN (electronic)978-1-6654-3654-0, 978-1-6654-3653-3
ISBN (print)978-1-6654-3655-7
Publication statusPublished - 2021
Peer-reviewedYes

Conference

Title16th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era
Abbreviated titleDTIS 2021
Conference number16
Duration28 - 30 June 2021
Website
LocationOnline
CityApulia
CountryItaly

External IDs

ORCID /0000-0003-3814-0378/work/142256167

Keywords

Keywords

  • FeFET design, Logic-in-Memory, Look up table, Non-volatile logic gates, TC-MEM, TCAM, Ternary content address memory