FDBench: A Paired Golden-Buggy Benchmark for FPGA Debugging

Research output: Contribution to book/Conference proceedings/Anthology/Report › Conference contribution › Contributed › peer-review

Abstract

Despite their wide use in digital and embedded systems, Field-Programmable Gate Array (FPGA) debugging remains challenging due to design complexity, limited observability, and inefficient trace analysis. The field still lacks a standard benchmark. This makes it hard for researchers to compare their work or verify what has already been done in FPGA debugging. We present a benchmark for FPGA debugging that includes typical bug cases, various fault types, configurable observability settings, and Integrated Logic Analyzer (ILA)-based reference baselines. The benchmark supports consistent and reproducible evaluation of FPGA debug systems and tools. It reduces the difficulty of FPGA debugging research and facilitates systematic comparison, reproducibility, and innovation in FPGA debugging system development.

Details

Original languageEnglish
Title of host publicationProceedings of the 16th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2026
EditorsRiadh Ben Abdelhamid, Ray Cheung, Frank Hannig, Shreejith Shanker, Dirk Koch, Shinya Takamaeda, Mirjana Stojilovic
PublisherAssociation for Computing Machinery (ACM)
Pages161-163
Number of pages3
ISBN (electronic)979-8-4007-2452-7
Publication statusPublished - 13 Aug 2026
Peer-reviewedYes

Conference

Title16th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies
Abbreviated titleHEART 2026
Conference number16
Duration17 - 19 June 2026
Website
LocationEuropean Institute for Neuromorphic Computing (EINC)
CityHeidelberg
CountryGermany

External IDs

ORCID /0000-0003-2571-8441/work/227511524
ORCID /0009-0008-7205-6667/work/227514169

Keywords

Keywords

  • Benchmark, Debugging Benchmark, Embedded Systems, FPGA Debugging, FPGA Systems, FPGA Verification