FDBench: A Paired Golden-Buggy Benchmark for FPGA Debugging

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/Gutachten › Beitrag in Konferenzband › Beigetragen › Begutachtung

Abstract

Despite their wide use in digital and embedded systems, Field-Programmable Gate Array (FPGA) debugging remains challenging due to design complexity, limited observability, and inefficient trace analysis. The field still lacks a standard benchmark. This makes it hard for researchers to compare their work or verify what has already been done in FPGA debugging. We present a benchmark for FPGA debugging that includes typical bug cases, various fault types, configurable observability settings, and Integrated Logic Analyzer (ILA)-based reference baselines. The benchmark supports consistent and reproducible evaluation of FPGA debug systems and tools. It reduces the difficulty of FPGA debugging research and facilitates systematic comparison, reproducibility, and innovation in FPGA debugging system development.

Details

OriginalspracheEnglisch
TitelProceedings of the 16th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2026
Redakteure/-innenRiadh Ben Abdelhamid, Ray Cheung, Frank Hannig, Shreejith Shanker, Dirk Koch, Shinya Takamaeda, Mirjana Stojilovic
Herausgeber (Verlag)Association for Computing Machinery (ACM)
Seiten161-163
Seitenumfang3
ISBN (elektronisch)979-8-4007-2452-7
PublikationsstatusVeröffentlicht - 13 Aug. 2026
Peer-Review-StatusJa

Konferenz

Titel16th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies
KurztitelHEART 2026
Veranstaltungsnummer16
Dauer17 - 19 Juni 2026
Webseite
OrtEuropean Institute for Neuromorphic Computing (EINC)
StadtHeidelberg
LandDeutschland

Externe IDs

ORCID /0000-0003-2571-8441/work/227511524
ORCID /0009-0008-7205-6667/work/227514169

Schlagworte

ASJC Scopus Sachgebiete

Schlagwörter

  • Benchmark, Debugging Benchmark, Embedded Systems, FPGA Debugging, FPGA Systems, FPGA Verification