Fail-Awareness: An Approach to Construct Fail-Safe Applications

Research output: Contribution to book/conference proceedings/anthology/reportConference contributionContributedpeer-review

Contributors

  • Christof Fetzer - , University of California at San Diego (Author)
  • Flaviu Cristian - , University of California at San Diego (Author)

Abstract

We present a framework for building fail-safe hard real-time applications on top of an asynchronous distributed system subject to communication partitions, i.e. using processors and communication facilities whose real-time delays cannot be guaranteed. The basic assumption behind our approach is that each processor has a local hardware clock that proceeds within a linear envelope of real-time. This allows to compute an upper bound on the actual delays incurred by a particular processing sequence or message transmission. Services and applications can use these computed bounds to detect when they cannot guarantee all their properties because of excessive delays. This allows an application to detect when to switch to a fail-safe mode.

Details

Original languageEnglish
Title of host publicationProceedings of IEEE 27th International Symposium on Fault Tolerant Computing
Pages282-291
Number of pages10
Publication statusPublished - 1997
Peer-reviewedYes
Externally publishedYes

Conference

Title7th Annual International Symposium on Fault-Tolerant Computing (FTCS 1997)
Abbreviated titleFTCS 1997
Conference number
Duration24 June 1997
Degree of recognitionInternational event
Location
CitySeattle
CountryUnited States of America

External IDs

Scopus 77957964515

Keywords

Research priority areas of TU Dresden

DFG Classification of Subject Areas according to Review Boards

Keywords

  • fail-safe systems, fail-awareness, timed asynchronous systems, synchronous systems, real time systems, switches, Delay, Application software, Upper bound, Force measurement, buildings, Clocks, reliability, communication partitionis, processing sequence, message transmission