Fail-Awareness: An Approach to Construct Fail-Safe Applications

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/GutachtenBeitrag in KonferenzbandBeigetragenBegutachtung

Beitragende

  • Christof Fetzer - , University of California at San Diego (Autor:in)
  • Flaviu Cristian - , University of California at San Diego (Autor:in)

Abstract

We present a framework for building fail-safe hard real-time applications on top of an asynchronous distributed system subject to communication partitions, i.e. using processors and communication facilities whose real-time delays cannot be guaranteed. The basic assumption behind our approach is that each processor has a local hardware clock that proceeds within a linear envelope of real-time. This allows to compute an upper bound on the actual delays incurred by a particular processing sequence or message transmission. Services and applications can use these computed bounds to detect when they cannot guarantee all their properties because of excessive delays. This allows an application to detect when to switch to a fail-safe mode.

Details

OriginalspracheEnglisch
TitelProceedings of IEEE 27th International Symposium on Fault Tolerant Computing
Seiten282-291
Seitenumfang10
PublikationsstatusVeröffentlicht - 1997
Peer-Review-StatusJa
Extern publiziertJa

Konferenz

Titel7th Annual International Symposium on Fault-Tolerant Computing (FTCS 1997)
KurztitelFTCS 1997
Veranstaltungsnummer
Dauer24 Juni 1997
BekanntheitsgradInternationale Veranstaltung
Ort
StadtSeattle
LandUSA/Vereinigte Staaten

Externe IDs

Scopus 77957964515

Schlagworte

Forschungsprofillinien der TU Dresden

DFG-Fachsystematik nach Fachkollegium

Schlagwörter

  • fail-safe systems, fail-awareness, timed asynchronous systems, synchronous systems, real time systems, switches, Delay, Application software, Upper bound, Force measurement, buildings, Clocks, reliability, communication partitionis, processing sequence, message transmission