Extraction of small-signal equivalent circuit for de-embedding of 3D vertical nanowire transistor
Research output: Contribution to journal › Research article › Contributed › peer-review
Contributors
Abstract
In this paper, we present an improved methodology to extract the small-signal electrical equivalent circuit of the parasitic elements using RF test structures for a 3D vertical nanowire transistor technology. The methodology is based on the extraction of the distributed parasitic elements from an open structure for which on-wafer S-parameter measurements were carried out up to 40 GHz. The electrical equivalent circuit of the passive device was then used for de-embedding of the transistor S-parameters for extraction of intrinsic small-signal parameters such as the gate capacitances.
Details
Original language | English |
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Article number | 108359 |
Journal | Solid-state electronics |
Volume | 194 |
Publication status | Published - Aug 2022 |
Peer-reviewed | Yes |
External IDs
Scopus | 85129599580 |
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Mendeley | f185f360-fc5d-3d3b-b396-3a4f2d391a70 |
unpaywall | 10.1016/j.sse.2022.108359 |
ORCID | /0000-0003-3814-0378/work/142256140 |
Keywords
Keywords
- Test structure, Equivalent circuit, Parasitic components, RF measurements, De-embedding