Extending Microprocessor Trace Hardware for Fault Injection
Research output: Contribution to book/Conference proceedings/Anthology/Report › Conference contribution › Contributed › peer-review
Contributors
Abstract
This paper proposes a novel concept for fault injection based on the trace interface, which is originally intended for software debugging. Initially, an introduction to fault injection is presented. Following the illustration of the underlying infrastructure, requirements for the integration of fault injection are developed leading to the selection of instrumentation-based techniques. On this basis, this document details the implementation of a technique on register transfer level, supporting five fault models. Controllability and observability of faults are specified.
Details
Original language | English |
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Title of host publication | 8. GMM/ITG/GI-Symposium Reliability by Design (ZuE) |
Number of pages | 8 |
Publication status | Published - 21 Sept 2015 |
Peer-reviewed | Yes |
Conference
Title | 8. GMM/ITG/GI-Symposium Reliability by Design |
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Abbreviated title | ZuE |
Conference number | |
Duration | 21 - 23 September 2015 |
Location | |
City | Siegen |
Country | Germany |