Extending Microprocessor Trace Hardware for Fault Injection

Research output: Contribution to book/conference proceedings/anthology/reportConference contributionContributedpeer-review

Abstract

This paper proposes a novel concept for fault injection based on the trace interface, which is originally intended for software debugging. Initially, an introduction to fault injection is presented. Following the illustration of the underlying infrastructure, requirements for the integration of fault injection are developed leading to the selection of instrumentation-based techniques. On this basis, this document details the implementation of a technique on register transfer level, supporting five fault models. Controllability and observability of faults are specified.

Details

Original languageEnglish
Title of host publication8. GMM/ITG/GI-Symposium Reliability by Design (ZuE)
Number of pages8
Publication statusPublished - 21 Sept 2015
Peer-reviewedYes

Conference

Title8. GMM/ITG/GI-Symposium Reliability by Design
Abbreviated titleZuE
Conference number
Duration21 - 23 September 2015
Location
CitySiegen
CountryGermany

Keywords

Research priority areas of TU Dresden