Exploring Standard-Cell Designs for Reconfigurable Nanotechnologies: A Formal Approach.
Research output: Contribution to book/Conference proceedings/Anthology/Report › Conference contribution › Contributed › peer-review
Contributors
Abstract
Standard-cell design has always been a craft, and common field-effect transistors
span only a small design space.
This has changed with reconfigurable transistors.
Boolean functions that exhibit multiple dual product-terms in their sum-of-product
form yield various beneficial circuit implementations with
reconfigurable transistors.
In this work, we present an approach to automatically generate these implementations
through a formal modeling approach.
Using the 3-input XOR function as an example, we discuss the variations and
show how to quantify properties like worst-case delay and power
dissipation, as well as averages of delay and energy consumption per operation
over different scenarios.
The quantification runs fully automated on charge transport network models
employing probabilistic model checking.
This yields exact results instead of approximations obtained from experiments and sampling.
The highlight of our work is that the proposed approach provides a comprehensive
early technology evaluation flow.
span only a small design space.
This has changed with reconfigurable transistors.
Boolean functions that exhibit multiple dual product-terms in their sum-of-product
form yield various beneficial circuit implementations with
reconfigurable transistors.
In this work, we present an approach to automatically generate these implementations
through a formal modeling approach.
Using the 3-input XOR function as an example, we discuss the variations and
show how to quantify properties like worst-case delay and power
dissipation, as well as averages of delay and energy consumption per operation
over different scenarios.
The quantification runs fully automated on charge transport network models
employing probabilistic model checking.
This yields exact results instead of approximations obtained from experiments and sampling.
The highlight of our work is that the proposed approach provides a comprehensive
early technology evaluation flow.
Details
Original language | English |
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Title of host publication | Proceedings of the 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022 |
Editors | Cristiana Bolchini, Ingrid Verbauwhede, Ioana Vatajelu |
Pages | 23-28 |
Number of pages | 6 |
ISBN (electronic) | 9783981926361 |
Publication status | Published - 2022 |
Peer-reviewed | Yes |
Conference
Title | 2022 Design, Automation and Test in Europe Conference and Exhibition, DATE 2022 |
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Duration | 14 - 23 March 2022 |
City | Virtual, Online |
Country | Belgium |
External IDs
Scopus | 85130816133 |
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Keywords
Research priority areas of TU Dresden
DFG Classification of Subject Areas according to Review Boards
Subject groups, research areas, subject areas according to Destatis
Sustainable Development Goals
ASJC Scopus subject areas
Keywords
- Circuit analysis, Formal Verification, Nanoelectronics, Probabilistic model checking, Probability, Quantitative Analysis, Reconfigurable logic, Semiconductor device modeling, probabilistic model checking, reconfigurable logic, probability, formal verification, semiconductor device modeling, nanoelectronics, quantitative analysis